SimpleOS

LXR

Navigation



Site hébergé par : enix

The LXR Cross Referencer for SOS

source navigation ]
diff markup ]
identifier search ]
general search ]
 
 
Article:1 ] [ 2 ] [ 3 ] [ 4 ] [ 5 ] [ 6 ] [ 6.5 ] [ 7 ] [ 7.5 ] [ 8 ] [ 9 ] [ 9.5 ]

Diff markup

Differences between /hwcore/idt.h (Article 8) and /hwcore/idt.h (Article 6.5)


001 /* Copyright (C) 2004  David Decotigny            001 /* Copyright (C) 2004  David Decotigny
002                                                   002 
003    This program is free software; you can redi    003    This program is free software; you can redistribute it and/or
004    modify it under the terms of the GNU Genera    004    modify it under the terms of the GNU General Public License
005    as published by the Free Software Foundatio    005    as published by the Free Software Foundation; either version 2
006    of the License, or (at your option) any lat    006    of the License, or (at your option) any later version.
007                                                   007    
008    This program is distributed in the hope tha    008    This program is distributed in the hope that it will be useful,
009    but WITHOUT ANY WARRANTY; without even the     009    but WITHOUT ANY WARRANTY; without even the implied warranty of
010    MERCHANTABILITY or FITNESS FOR A PARTICULAR    010    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
011    GNU General Public License for more details    011    GNU General Public License for more details.
012                                                   012    
013    You should have received a copy of the GNU     013    You should have received a copy of the GNU General Public License
014    along with this program; if not, write to t    014    along with this program; if not, write to the Free Software
015    Foundation, Inc., 59 Temple Place - Suite 3    015    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307,
016    USA.                                           016    USA. 
017 */                                                017 */
018 #ifndef _SOS_IDT_H_                               018 #ifndef _SOS_IDT_H_
019 #define _SOS_IDT_H_                               019 #define _SOS_IDT_H_
020                                                   020 
021 /**                                               021 /**
022  * @file idt.h                                    022  * @file idt.h
023  *                                                023  *
024  * Manage the x86 Interrupt Descriptor Table,     024  * Manage the x86 Interrupt Descriptor Table, the table which maps the
025  * hardware interrupt lines, hardware exceptio    025  * hardware interrupt lines, hardware exceptions, and software
026  * interrupts, to software routines. We only d    026  * interrupts, to software routines. We only define "interrupt gate"
027  * IDT entries. Don't use it directly; refer i    027  * IDT entries. Don't use it directly; refer instead to interrupt.c,
028  * exceptions.c and syscall.c.                    028  * exceptions.c and syscall.c.
029  *                                                029  *
030  * @see Intel x86 doc, Vol 3, chapter 5           030  * @see Intel x86 doc, Vol 3, chapter 5
031  */                                               031  */
032                                                   032 
033 #include <sos/errno.h>                            033 #include <sos/errno.h>
034 #include <sos/types.h>                            034 #include <sos/types.h>
035                                                   035 
036 /* Mapping of the CPU exceptions in the IDT (i    036 /* Mapping of the CPU exceptions in the IDT (imposed by Intel
037    standards) */                                  037    standards) */
038 #define SOS_EXCEPT_BASE 0                         038 #define SOS_EXCEPT_BASE 0
039 #define SOS_EXCEPT_NUM  32                        039 #define SOS_EXCEPT_NUM  32
040 #define SOS_EXCEPT_MAX  (SOS_HWEXCEPT_BASE + S    040 #define SOS_EXCEPT_MAX  (SOS_HWEXCEPT_BASE + SOS_HWEXCEPT_NUM - 1)
041                                                   041 
042 /* Mapping of the IRQ lines in the IDT */         042 /* Mapping of the IRQ lines in the IDT */
043 #define SOS_IRQ_BASE    32                        043 #define SOS_IRQ_BASE    32
044 #define SOS_IRQ_NUM     16                        044 #define SOS_IRQ_NUM     16
045 #define SOS_IRQ_MAX     (SOS_IRQ_BASE + SOS_IR    045 #define SOS_IRQ_MAX     (SOS_IRQ_BASE + SOS_IRQ_NUM - 1)
046                                                   046 
047 /**                                               047 /**
048  * Number of IDT entries.                         048  * Number of IDT entries.
049  *                                                049  *
050  * @note Must be large enough to map the hw in    050  * @note Must be large enough to map the hw interrupts, the exceptions
051  * (=> total is 48 entries), and the syscall(s    051  * (=> total is 48 entries), and the syscall(s). Since our syscall
052  * will be 0x42, it must be >= 0x43. Intel doc    052  * will be 0x42, it must be >= 0x43. Intel doc limits this to 256
053  * entries, we use this limit.                    053  * entries, we use this limit.
054  */                                               054  */
055 #define SOS_IDTE_NUM      256 /* 0x100 */         055 #define SOS_IDTE_NUM      256 /* 0x100 */
056                                                   056 
057 /** Initialization routine: all the IDT entrie    057 /** Initialization routine: all the IDT entries (or "IDTE") are marked
058     "not present". */                             058     "not present". */
059 sos_ret_t sos_idt_subsystem_setup(void);          059 sos_ret_t sos_idt_subsystem_setup(void);
060                                                   060 
061 /**                                               061 /**
062  * Enable the IDT entry if handler_address !=     062  * Enable the IDT entry if handler_address != NULL, with the given
063  * lowest_priviledge.\ Disable the IDT entry w    063  * lowest_priviledge.\ Disable the IDT entry when handler_address ==
064  * NULL (the lowest_priviledge parameter is th    064  * NULL (the lowest_priviledge parameter is then ignored). Intel doc
065  * says that there must not be more than 256 e    065  * says that there must not be more than 256 entries.
066  *                                                066  *
067  * @note IRQ Unsafe                               067  * @note IRQ Unsafe
068  */                                               068  */
069 sos_ret_t sos_idt_set_handler(int index,          069 sos_ret_t sos_idt_set_handler(int index,
070                               sos_vaddr_t hand    070                               sos_vaddr_t handler_address,
071                               int lowest_privi    071                               int lowest_priviledge /* 0..3 */);
072                                                   072 
073                                                   073 
074 /**                                               074 /**
075  * @note IRQ Unsafe                               075  * @note IRQ Unsafe
076  *                                                076  *
077  * @return the handler address and DPL in the     077  * @return the handler address and DPL in the 2nd and 3rd
078  * parameters                                     078  * parameters
079  */                                               079  */
080 sos_ret_t sos_idt_get_handler(int index,          080 sos_ret_t sos_idt_get_handler(int index,
081                               sos_vaddr_t *han    081                               sos_vaddr_t *handler_address,
082                               int *lowest_priv    082                               int *lowest_priviledge);
083                                                   083 
084 #endif /* _SOS_IDT_H_ */                          084 #endif /* _SOS_IDT_H_ */
                                                      

source navigation ] diff markup ] identifier search ] general search ]