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001 /* Copyright (C) 2004 David Decotigny 001 /* Copyright (C) 2004 David Decotigny >> 002 Copyright (C) 1999 Free Software Foundation, Inc. 002 003 003 This program is free software; you can redi 004 This program is free software; you can redistribute it and/or 004 modify it under the terms of the GNU Genera 005 modify it under the terms of the GNU General Public License 005 as published by the Free Software Foundatio 006 as published by the Free Software Foundation; either version 2 006 of the License, or (at your option) any lat 007 of the License, or (at your option) any later version. 007 008 008 This program is distributed in the hope tha 009 This program is distributed in the hope that it will be useful, 009 but WITHOUT ANY WARRANTY; without even the 010 but WITHOUT ANY WARRANTY; without even the implied warranty of 010 MERCHANTABILITY or FITNESS FOR A PARTICULAR 011 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 011 GNU General Public License for more details 012 GNU General Public License for more details. 012 013 013 You should have received a copy of the GNU 014 You should have received a copy of the GNU General Public License 014 along with this program; if not, write to t 015 along with this program; if not, write to the Free Software 015 Foundation, Inc., 59 Temple Place - Suite 3 016 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, 016 USA. 017 USA. 017 */ 018 */ 018 #ifndef _SOS_IDT_H_ 019 #ifndef _SOS_IDT_H_ 019 #define _SOS_IDT_H_ 020 #define _SOS_IDT_H_ 020 021 021 /** 022 /** 022 * @file idt.h 023 * @file idt.h 023 * 024 * 024 * Manage the x86 Interrupt Descriptor Table, 025 * Manage the x86 Interrupt Descriptor Table, the table which maps the 025 * hardware interrupt lines, hardware exceptio 026 * hardware interrupt lines, hardware exceptions, and software 026 * interrupts, to software routines. We only d 027 * interrupts, to software routines. We only define "interrupt gate" 027 * IDT entries. Don't use it directly; refer i 028 * IDT entries. Don't use it directly; refer instead to interrupt.c, 028 * exceptions.c and syscall.c. 029 * exceptions.c and syscall.c. 029 * 030 * 030 * @see Intel x86 doc, Vol 3, chapter 5 031 * @see Intel x86 doc, Vol 3, chapter 5 031 */ 032 */ 032 033 033 #include <sos/errno.h> 034 #include <sos/errno.h> 034 #include <sos/types.h> 035 #include <sos/types.h> 035 036 036 /* Mapping of the CPU exceptions in the IDT (i 037 /* Mapping of the CPU exceptions in the IDT (imposed by Intel 037 standards) */ 038 standards) */ 038 #define SOS_EXCEPT_BASE 0 039 #define SOS_EXCEPT_BASE 0 039 #define SOS_EXCEPT_NUM 32 040 #define SOS_EXCEPT_NUM 32 040 #define SOS_EXCEPT_MAX (SOS_HWEXCEPT_BASE + S 041 #define SOS_EXCEPT_MAX (SOS_HWEXCEPT_BASE + SOS_HWEXCEPT_NUM - 1) 041 042 042 /* Mapping of the IRQ lines in the IDT */ 043 /* Mapping of the IRQ lines in the IDT */ 043 #define SOS_IRQ_BASE 32 044 #define SOS_IRQ_BASE 32 044 #define SOS_IRQ_NUM 16 045 #define SOS_IRQ_NUM 16 045 #define SOS_IRQ_MAX (SOS_IRQ_BASE + SOS_IR 046 #define SOS_IRQ_MAX (SOS_IRQ_BASE + SOS_IRQ_NUM - 1) 046 047 047 /** 048 /** 048 * Number of IDT entries. 049 * Number of IDT entries. 049 * 050 * 050 * @note Must be large enough to map the hw in 051 * @note Must be large enough to map the hw interrupts, the exceptions 051 * (=> total is 48 entries), and the syscall(s 052 * (=> total is 48 entries), and the syscall(s). Since our syscall 052 * will be 0x42, it must be >= 0x43. Intel doc 053 * will be 0x42, it must be >= 0x43. Intel doc limits this to 256 053 * entries, we use this limit. 054 * entries, we use this limit. 054 */ 055 */ 055 #define SOS_IDTE_NUM 256 /* 0x100 */ 056 #define SOS_IDTE_NUM 256 /* 0x100 */ 056 057 057 /** Initialization routine: all the IDT entrie 058 /** Initialization routine: all the IDT entries (or "IDTE") are marked 058 "not present". */ 059 "not present". */ 059 sos_ret_t sos_idt_subsystem_setup(void); !! 060 sos_ret_t sos_idt_setup(void); 060 061 061 /** 062 /** 062 * Enable the IDT entry if handler_address != 063 * Enable the IDT entry if handler_address != NULL, with the given 063 * lowest_priviledge.\ Disable the IDT entry w 064 * lowest_priviledge.\ Disable the IDT entry when handler_address == 064 * NULL (the lowest_priviledge parameter is th 065 * NULL (the lowest_priviledge parameter is then ignored). Intel doc 065 * says that there must not be more than 256 e 066 * says that there must not be more than 256 entries. 066 * 067 * 067 * @note IRQ Unsafe 068 * @note IRQ Unsafe 068 */ 069 */ 069 sos_ret_t sos_idt_set_handler(int index, 070 sos_ret_t sos_idt_set_handler(int index, 070 sos_vaddr_t hand 071 sos_vaddr_t handler_address, 071 int lowest_privi 072 int lowest_priviledge /* 0..3 */); 072 073 073 074 074 /** 075 /** 075 * @note IRQ Unsafe 076 * @note IRQ Unsafe 076 * 077 * 077 * @return the handler address and DPL in the 078 * @return the handler address and DPL in the 2nd and 3rd 078 * parameters 079 * parameters 079 */ 080 */ 080 sos_ret_t sos_idt_get_handler(int index, 081 sos_ret_t sos_idt_get_handler(int index, 081 sos_vaddr_t *han 082 sos_vaddr_t *handler_address, 082 int *lowest_priv 083 int *lowest_priviledge); 083 084 084 #endif /* _SOS_IDT_H_ */ 085 #endif /* _SOS_IDT_H_ */
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